科技创新，流程完善，以人为本，福利丰厚
Responsibilities：1.Module level UVM development2.Support testbench development3.Maintenance with failure analysis and resolution4.Help with coverage analysis and population5.Constraint-randomtest generation, and flow development Required Knowledge, Skills, Experience and Abilities：1.Must be pursuing a MSEE/MSCE2.Strong background in HDLs (e.g. Verilog) and HVLs (e.g. SystemVerilog/UVM, Vera, e) Preferred Knowledge, Skills, Experience and Abilities：1.scripting (e.g. Perl, Python, Unix/Linux shell)2.Knowledge of AXI, PIPE, video protocol3.Object oriented programming (e.g. SystemVerilog)